Optimizing Two - Phase , Level

We investigate two strategies for reducing the clock period of a two-phase, level-clocked circuit: clock tuning, which adjusts the waveforms that clock the circuit, and retiming, which relocates circuit latches. These methods can be used to convert a circuit with edge-triggered latches into a faster level-clocked one. We model a two-phase circuit as a graph whose vertex set V is a collection of combinational logic blocks, and whose edge set E is a set of interconnections. Each interconnection passes through 0 or more latches, where each latch is clocked by one of two periodic, nonoverlapping waveforms, or phases. We give eecient polynomial-time algorithms for problems involving the timing veriication and optimization of two-phase circuitry. Included are algorithms for verifying proper timing: O(V E) time. minimizing the clock period using clock tuning: O(V E) time. retiming to achieve a given clock period when the phases are symmetric: O(V E + V 2 lg V) time. retiming to achieve a given clock period when either the duty cycle (high time) of one phase or the ratio of the phases' duty cycles is xed: O(V 3) time. By characterizing the set of possible clock periods under any retiming of the circuit, we are able to obtain polynomial-time algorithms for clock period minimization by retiming when the phases are symmetric: O(V 2 E) time. retiming when either the duty cycle of one phase is xed or the ratio of the phases' duty cycles is xed: O(V 2 E + V 3 lgV) time. simultaneous retiming and clock tuning: O(V 11) time. Obviously, this last algorithm is not practical. For this problem, however, we give a fully polynomial-time approximation scheme that achieves the optimal period to within any given relative error bound e > 0 and runs in O(V 3 (1=e) lg(1=e)+(V E + V 2 lg V) lg(V=e)) time. We also give fully polynomial-time approximation schemes for the rst two of these three period-minimization retiming problems. These two algorithms run in O((V E + V 2 lg V) lg(V=e)) and O(V 3 lg(V=e)) time, respectively, and can be used to obtain the optimum clock period in the special case where all propagation delays are integers. We generalize most of the results for two-phase clocking schemes to simple mul-tiphase clocking disciplines, including ones with overlapping phases. Typically, the algorithms to verify and optimize the timing of k-phase circuits are at most a factor of k …